ARM Technology Access Partnership
YOGITECH's distinguishing expertise in the ARM Community is its verification and design for robustness competencies, especially for automotive applications. Belonging to the ARM Connected Community, the ARM Technology Access Partners (ATAPs) is a network of independent IC design centres, seven of which are in Europe, audited and approved by ARM according to their competence and experience. ATAPs have direct access to ARM technical support and are constantly updated to ARM's design kits, tools, processor models and debug environments. YOGITECH was appointed an ATAP in Q4 of 2001 and it was the first ATAP in Italy.



Open Choice Program
YOGITECH is part of the OpenChoice program that enables interoperability and facilitates open collaboration with leading IP providers to build, validate, and deliver accurate models for Cadence design and verification solutions.
The program aims to ensure IP quality, integration, and provides engineers access to a broad IP offering through a complete IP catalog. This optimizes the electronics design chain and accelerates customer time to market.


Cadence Verification Alliance
YOGITECH is a Cadence Incisive Plan-to-Closure Methodology–Qualified
Verification Alliance member and has demonstrated expertise in one or more
of the methodology’s four key elements: verification planning and
management, the Universal Reuse Methodology, assertion-based and formal
verification, and/or system-level verification.



OCP International Partnership
YOGITECH is a Sponsor Member of OCP International Partnership (OCP-IP), a non-profit semiconductor industry consortium created to administer the support, promotion and enhancement of the Open Core Protocol (OCP).
OCP is the only fully supported, openly licensed, complete interface socket for intellectual property (IP) cores.



Spirit Consortium
YOGITECH is Review Member of Spirit Consortium, an industry level cooperation in developing standards for IP description as well as tools to raise automation levels, cut costs, improve ease-of-use, increase flexibility in IP selection and integration. The consortium covers EDA tool vendors, IP providers and integrated device manufacturers involving many leading names in the IP supply chain.