Recent statistics showed that 60-70% of the entire product cycle for a complex logic chip is dedicated to verification tasks: 71% of SoC re-spins are due to logic bugs, and 47% of them are due to incorrect or incomplete specifications. Moreover, 14% of failing SoCs have bugs in reused components or IPs. Traditional verification methodologies (direct testing) have been proven to be inadequate to recognize all bugs because of the multiple possible verification cases. Therefore, verification efforts increase exponentially with the complexity of systems and with the design size.

YOGITECH's Verification team can solve any system or module level verification problem thanks to its consolidated and worldwide recognized experience in the use of random constraint-driven and coverage-driven methodology based on Cadence's VPA solutions.
YOGITECH integrates other cutting-edge methodologies, such as static or pseudo-static functional verification or co-verification with SW or SystemC.
In addition to its own Verification IPs, YOGITECH can be commissioned to design dedicated eVCs to match specific customer requirements.