| Pisa, Italia - YOGITECH participates at CDNLive!
Silicon Valley 2007, the event that will take place in San Jose,
CA, on Sept 10-12 2007.
During the event, Monia Chiavacci, Mixed Signal Team Leader
of YOGITECH, will give the speech «Coverage-Driven
AMS Verification of a 4Mb Z-RAM Macro» in the functional
verification track on Tuesday Sept 11 at 2.40 PM.
YOGITECH’s Analogue Mixed Signal Verification Kit (AMSvkit)
was used for the verification of a memory macro and the results
will be jointly presented with Innovative Silicon Inc., owner of
Z-RAM® memory technology.
The AMSvkit provides a methodology and a flow capable
to provide a rigorous checking on both digital and analogue signals
while extending into the analogue domain the concept of functional
coverage by means of a fully automated verification environment
based on Cadence Specman Elite and a mixed signal simulator. Such
methodology allows the coverage of verification holes usually left
uncovered at the interface of the digital and analogue areas by
the adoption of traditional approaches generally based on a sharp
separation between analogue simulation and digital functional verification.
This is becoming more and more crucial in the verification of memory
modules, where the interface between digital and analogue domains
is spread in the entire circuit (digital information is stored
in analogue format inside each bit cell) and the timing performances
play a decisive role. An effective and efficient mixed signal verification
environment must allow the use of a large number of vectors during
simulation while rigorously measuring and reporting analogue parameters
and quality metrics across a large portion of the design.
Quantitative and qualitative results will be presented showing meaningful
achievements in terms of performance, functional verification coverage,
easy of use, modularity and re-use.
ABOUT AMSvkit
www.amsvkit.yogitech.com
ABOUT Z-RAM®
www.innovativesilicon.com/technology_overview.php
ABOUT CDNLive!
www.cadence.com/cdnlive
ABOUT YOGITECH
YOGITECH is a company with proven experience in System-on-Chip,
Mixed-Signal design&verification, and fault-tolerant integrated
circuits. Founded in 2000, YOGITECH leverages unique expertise in
Specman Elite to provide sophisticated e and SystemVerilog Verification
Components to the market.
Sponsor Member of the OCP-IP consortium, YOGITECH is an active member
of the Cadence OpenChoice Partnership and Verification Alliance.
YOGITECH is also a member of the Spirit Consortium and an ARM Technology
Access Partner.
YOGITECH offers a catalogue of eRM Verification Components
to shorten time-to production of Intellectual Property cores and
SOC designs based on standard protocols such as OCP, ATAPI, CAN
and LIN. Additionally, YOGITECH offers the Analogue Mixed-Signal
Verification Kit (AMSvkit), a unique solution for
the verification of mixed-signal circuits and systems.
Today, world leaders in the semiconductor industry rely on YOGITECH’s
solutions and services.
CONTACT
Alessia Bandini
YOGITECH SPA
Public Relations
alessia.bandini@yogitech.com
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