YOGITECH, founded in 2000, is a company with a solid and proven experience in the design and verification of digital and mixed-signal System-on-Chip and in fault-tolerant integrated circuits. Headquartered in Pisa with offices in Nice, YOGITECH is an independent company with a Share Capital of 450 thousands Euros, privately owned by its founders and by financial partners such as Sici Toscana Venture Fund and the Chamber of Commerce of Pisa.

YOGITECH offers a catalogue of Verification IPs to shorten time-to-production of projects based on standard protocols, like ATAPI, LIN and CAN. The portfolio also includes the Analog Mixed Signal Verification Kit (AMSvKit) and the OCP 2.1 eVC, the only complete solution currently available in the market for the verification of OCP based modules and systems, successfully adopted by major semiconductor companies in Europe, US and Asia.

YOGITECH is part of the Cadence OpenChoice Program, ARM Technology Access Partner, Sponsor Member of the OCP-IP and Review Member of Spirit Consortium.

Silvano Motto
President - Chief Executive Officer
Graduated in Electronic Engineering at the University of Pisa, Silvano was Associated Fellow at CERN (Geneva, CH) and Research Assistant of the Signal Processing Laboratory at the Technological University of Tampere, Finland.
He has been Marketing Manager in Italian microelectronics oriented SME, then he founded YOGITECH in August 2000 and he chaired the Board since then.
Silvano is also European Community Evaluator in the Sixth Framework Programme, after having been in the Fifth. He was also Member of VTS2000 and VTS2002 (IEEE VLSI Test Symposium) Program Committee, Member of ETW 99 (European Test Workshop 1999) Program Committee.

Riccardo Mariani
Chief Technology Officer
Riccardo Mariani holds a Ph.D. in Microelectronics from
the University of Pisa. Before founding YOGITECH, he was Technical Director in Aurelia Microelettronica, CAD Laboratory and Team Director in CAEN Microelettronica,
Digital Design Responsible and CAD Laboratory Coordinator in Centro TEAM, Digital Design Consultant in Italtel Center of Parma University.
Riccardo won SGS-Thomson and Enrico Denoth Best Engineering Award. He is IEEE member and he has authored many papers related to High-Reliability Circuits, Design for Testability, Advanced Design Techniques and Asynchronous Circuits.

Gabriele Orlandi
General Manager
Graduated in Physics at the University of Torino, Gabriele was trained in Finance and Business Administration at SDA Bocconi (Milan). After five years of R&D activity in the Technology Division at CERN, European Laboratory for Particle Physics in Geneva, Gabriele moved to consultancy experience as Technology Manager in R&D Institutions and as Business Developer for high-tech companies.
He joined YOGITECH on a full-time appointment during 2002, as Director of Finance.

Stefano Lorenzini
Design Engineering Manager
Graduated in Microelectronics at University of Pisa (1992), Stefano has gathered more than twelve years of experience in high-end semiconductors industries.
He worked for Marconi Communication as a team member of the ASIC/FPGA methodology group. Then he moved to Alcatel Microelectronics, successfully leading challenging designs in the telecom area, such as SDH ADM and ADSL Central Office modems. Before joining YOGITECH, Stefano worked as a team leader for ST Microelectronics where he managed important ADSL and Gateway programs based on embedded multiprocessors and custom DSPs.
He joined YOGITECH during 2005.

ARM Technology Access Partnership
YOGITECH's distinguishing expertise in the ARM Community is its verification and design for robustness competencies, especially for automotive applications. Belonging to the ARM Connected Community, the ARM Technology Access Partners (ATAPs) is a network of independent IC design centres, seven of which are in Europe, audited and approved by ARM according to their competence and experience. ATAPs have direct access to ARM technical support and are constantly updated to ARM's design kits, tools, processor models and debug environments. YOGITECH was appointed an ATAP in Q4 of 2001 and it was the first ATAP in Italy.



Open Choice Program
YOGITECH is part of the OpenChoice program that enables interoperability and facilitates open collaboration with leading IP providers to build, validate, and deliver accurate models for Cadence design and verification solutions.
The program aims to ensure IP quality, integration, and provides engineers access to a broad IP offering through a complete IP catalog. This optimizes the electronics design chain and accelerates customer time to market.


Cadence Verification Alliance
YOGITECH is a Cadence Incisive Plan-to-Closure Methodology–Qualified
Verification Alliance member and has demonstrated expertise in one or more
of the methodology’s four key elements: verification planning and
management, the Universal Reuse Methodology, assertion-based and formal
verification, and/or system-level verification.



OCP International Partnership
YOGITECH is a Sponsor Member of OCP International Partnership (OCP-IP), a non-profit semiconductor industry consortium created to administer the support, promotion and enhancement of the Open Core Protocol (OCP).
OCP is the only fully supported, openly licensed, complete interface socket for intellectual property (IP) cores. YOGITECH’s products portfolio includes OCP 2.1 eVC, the only complete solution for verifying OCP systems which is successfully adopted by major semiconductor companies in Europe, US and Asia.



Spirit Consortium
YOGITECH is Review Member of Spirit Consortium, an industry level cooperation in developing standards for IP description as well as tools to raise automation levels, cut costs, improve ease-of-use, increase flexibility in IP selection and integration. The consortium covers EDA tool vendors, IP providers and integrated device manufacturers involving many leading names in the IP supply chain.

YOGITECH is addressing its products offering on three main streams leveraging the expertise acquired in design and verification support activities along the years.

The Verification IPs (VIPs) catalogue is currently based on the functional verification methodology provided by Specman Elite, but an extension of the catalogue to different methodologies and verification languages like SystemVerilog are in the roadmap. The catalogue includes VIPs for CAN 2.0A/B and LIN 2.0 (automotive applications), ATAPI (storage applications) and OCP 2.1 (set-top box, printers, games, video recorders, mobile phones, DTV, wireless LAN). More VIPs will be added by the end of the year.

The Analog Mixed Signal Verification Kit (AMSvKit) is a very innovative approach that allows a meaningful step forward in the verification of analog mixed signal applications overcoming the drawbacks of traditional approaches. It includes an extensible set of configurable, plug-and-play pre-verified verification components that unify Specman Elite and most popular mixed-signal simulators to create an Object-Oriented mixed-signal functional verification environment.

faultRobust is the innovative technology for addressing and achieving fault robustness in Integrated Circuits. It provides a set of IPs, tools and methodologies for the detection and correction of faults affecting the different parts of the electronic equipment or SoC. The emerging safety norm IEC61508 is addressed and all of the different parts composing the technology are under the certification process of TÜV-SÜD. Automotive active and passive safety systems such as Steer-by-wire, Brake-by-wire, ABS, etc. or more in general applications requiring a high degree of reliability can dramatically benefit by including faultRobust.

Electronic systems are nowadays the result of the convergence of different technologies. Therefore a combination of experience, techniques, tools and a proper contact network is mandatory to meet market expectations.
By working with YOGITECH, customers leverage on the company's solid partnership with top-tier EDA tool vendors. Years of experience dealing with world-wide customers and a proven track of right-first-time designs make
YOGITECH reliable for any kind of IC design.

Projects at YOGITECH are managed by specifications, timescale and budget, previously agreed with clients. This disciplined yet flexible approach combines with YOGITECH's methodology, skills and know-how, delivering customer satisfaction and business renewal. YOGITECH is actively involved in SoCs or ASICs design&verification, including implementation or re-use of IP blocks (digital, analogue and verification), providing point solutions and filling resource shortfall.

Systems-on-Chip are one of the biggest challenges engineers ever faced. They are the result of a mix of microprocessors, memories, busses, architectures, communication standards, protocol processors, interfaces
and other intellectual property components where system level considerations such as power optimization, synchronisation, testability, conformance and verification are crucial.

YOGITECH's outstanding experience with CPUs interconnect standards and protocols make it easier to match all system requirements. YOGITECH’s approach always begins with a fully detailed verification plan and it is based on a strong interaction between digital and analogue expertises and the use of the most advanced verification techniques.

YOGITECH's involvement into a project can span from specs to tape out (all intermediate steps included), working independently or in team with the customer. YOGITECH's expertise includes design of customized IPs providing highest-quality deliverables such as datasheets, characterization layout constraints, coverage reports, implementation, verification scripts. YOGITECH’s design track record includes projects for the global worldwide leaders SIPs and OEMs in the automotive, biomedical and telecom sector.

Today's Application Specific Integrated Circuits (ASIC) include analogue
front-ends, A/D and D/A, transceivers, tightly coupled with digital signal processing, memories and protocol engines. High precision analogue blocks are often close to high speed and noisy digital parts driving high voltage drivers. A comprehensive approach on specification, design, verification and testing is therefore needed to manage such increasing complexity.

YOGITECH has a consolidated experience in defining system requirements and a deep understanding of standards. These outstanding skills in system modelling allow YOGITECH to translate applications needs into ASIC specifications for a wide range of technologies from deep sub-micron (0.13µm) to 100V DMOS processes.

YOGITECH's Mixed-Signal verification approach combines classical methods based on mix-mode simulations with state-of-the-art functional verification techniques. YOGITECH’s success stories include IC designed for automotive, biomedics, telecom and consumer, with a design track record that includes most important world-wide SIPs and OEMs.

Recent statistics showed that 60-70% of the entire product cycle for a complex logic chip is dedicated to verification tasks: 71% of SoC re-spins are due to logic bugs, and 47% of them are due to incorrect or incomplete specifications. Moreover, 14% of failing SoCs have bugs in reused components or IPs. Traditional verification methodologies (direct testing) have been proven to be inadequate to recognize all bugs because of the multiple possible verification cases. Therefore, verification efforts increase exponentially with the complexity of systems and with the design size.

YOGITECH's Verification team can solve any system or module level verification problem thanks to its consolidated and worldwide recognized experience in the use of random constraint-driven and coverage-driven methodology based on Cadence's VPA solutions.
YOGITECH integrates other cutting-edge methodologies, such as static or pseudo-static functional verification or co-verification with SW or SystemC.
In addition to its own Verification IPs, YOGITECH can be commissioned to design dedicated eVCs to match specific customer requirements.