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YOGITECH, founded in 2000, is a
company with a solid and proven experience in the design and
verification of digital and mixed-signal System-on-Chip and in
fault-tolerant integrated circuits. Headquartered in Pisa with offices
in Nice, YOGITECH is an independent company with a Share Capital of 450
thousands Euros, privately owned by its founders and by financial
partners such as Sici Toscana Venture Fund and the Chamber of Commerce
of Pisa.
YOGITECH offers the Analogue Mixed-Signal Verification Kit (AMSvKit),
a unique solution for the verification of mixed-signal circuits and
systems. Today, world leaders in the semiconductor industry rely on
YOGITECH’s verification solutions and services. Additionally,
YOGITECH offers faultRobust, the
technology for addressing and achieving fault robustness in Integrated
Circuits.
YOGITECH is part of the Cadence OpenChoice Program, ARM Technology
Access Partner, Sponsor Member of the OCP-IP and Review Member of
Spirit Consortium.
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ARM Technology Access
Partnership
YOGITECH's distinguishing expertise in the ARM Community is its
verification and design for robustness competencies, especially for
automotive applications. Belonging to the ARM Connected Community, the
ARM Technology Access Partners (ATAPs) is a network of independent IC
design centres, seven of which are in Europe, audited and approved by
ARM according to their competence and experience. ATAPs have direct
access to ARM technical support and are constantly updated to ARM's
design kits, tools, processor models and debug environments. YOGITECH
was appointed an ATAP in Q4 of 2001 and it was the first ATAP in Italy.
Open Choice Program
YOGITECH is part of the
OpenChoice program that enables interoperability and facilitates open
collaboration with leading IP providers to build, validate, and deliver
accurate models for Cadence design and verification solutions.
The program aims to ensure IP quality, integration, and provides
engineers access to a broad IP offering through a complete IP catalog.
This optimizes the electronics design chain and accelerates customer
time to market.
Cadence Verification Alliance
YOGITECH is a Cadence Incisive
Plan-to-Closure Methodology–Qualified
Verification Alliance member and has demonstrated expertise in one or
more
of the methodology’s four key elements: verification planning
and
management, the Universal Reuse Methodology, assertion-based and formal
verification, and/or system-level verification.
OCP
International Partnership
YOGITECH is a Sponsor Member of
OCP International Partnership (OCP-IP), a non-profit semiconductor
industry consortium created to administer the support, promotion and
enhancement of the Open Core Protocol (OCP).
OCP is the only fully supported, openly licensed, complete interface
socket for intellectual property (IP) cores.
Spirit Consortium
YOGITECH is Review Member of
Spirit Consortium, an industry level cooperation in developing
standards for IP description as well as tools to raise automation
levels, cut costs, improve ease-of-use, increase flexibility in IP
selection and integration. The consortium covers EDA tool vendors, IP
providers and integrated device manufacturers involving many leading
names in the IP supply chain.
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 P R O D U C T S |
 faultRobust |
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YOGITECH's
faultRobust is
the technology for addressing and achieving fault robustness in
Integrated Circuits.
It provides a set of IPs, tools and methodologies for the detection and
correction of faults affecting the different parts of the electronic
equipment or SOC. Each fRIP can be
stand-alone, protecting a particular component such as CPU, memory
system and peripherals, or it can be combined with other fRIPs
for a complete solution.
YOGITECH's faultRobust technology
optimizes costs by minimizing gate count, software overhead and power
consumption; it reduces the common mode effects by adding diversity; it
minimizes performance impact; offering a platform-based modular and
reusable approach; it increases diagnostic capability; and it addresses
the emerging norm IEC 61508, thus providing
guidelines and a methodology for a system to be IEC 61508 adherent.
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YOGITECH's
Analog Mixed Signal Verification Kit (AMSvkit)
enables an automated, coverage-driven verification environment and
methodology for top-and block-level mixed-signal designs. The AMSvKit
comprises an extensible set of configurable, plug-and-play pre-verified
verification components that unify Specman Elite and a mixed-signal
simulator to create an Object-Oriented mixed-signal functional
verification environment.
The greatest obstacle to a System-on-Chip design team's success is
verification. Combine the challenges of
digital verification with the increasing integration of larger and more
sophisticated analog circuits and the problem is getting exponentially
worse. This trend not only presents a challenge to the verification
engineer, but to the industry as a whole.
To date, the use of hand-coded models of manually-verified analog
blocks within a digital verification environment has been sufficient to
provide confidence in a mixed-signal design to sign-off prior to
submitting it for fabrication. However, due to greater levels of
integration, changes in process technology and increasing market
pressures and risks, an automated and metric-driven methodology is now
required.
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Electronic systems are nowadays the
result of the convergence of different technologies. Therefore a
combination of experience, techniques, tools and a proper contact
network is mandatory to meet market expectations.
By working with YOGITECH, customers leverage on the company's solid
partnership with top-tier EDA tool vendors. Years of experience dealing
with world-wide customers and a proven track of right-first-time
designs make
YOGITECH reliable for any kind of IC design.
Projects at YOGITECH are managed by specifications, timescale and
budget, previously agreed with clients. This disciplined yet flexible
approach combines with YOGITECH's methodology, skills and know-how,
delivering customer satisfaction and business renewal. YOGITECH is
actively involved in SoCs or ASICs design&verification,
including implementation or re-use of IP blocks (digital,
analogue and verification), providing point solutions and
filling resource shortfall.
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 S E R V I C E S |
 System-on-Chip |
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Systems-on-Chip are one of the biggest
challenges engineers ever faced. They are the result of a mix of
microprocessors, memories, busses, architectures, communication
standards, protocol processors, interfaces
and other intellectual property components where system level
considerations such as power optimization, synchronisation,
testability, conformance and verification are crucial.
YOGITECH's outstanding experience with CPUs interconnect standards and
protocols make it easier to match all system requirements.
YOGITECH’s approach always begins with a fully detailed
verification plan and it is based on a strong interaction between
digital and analogue expertises and the use of the most advanced
verification techniques.
YOGITECH's involvement into a project can span from specs to tape out (all
intermediate steps included), working independently or in
team with the customer. YOGITECH's expertise includes design of
customized IPs providing highest-quality deliverables such as
datasheets, characterization layout constraints, coverage reports,
implementation, verification scripts. YOGITECH’s design track
record includes projects for the global worldwide leaders SIPs and OEMs
in the automotive, biomedical and telecom sector.
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| Take
a look at this section's pages to learn the latest news about YOGITECH,
what the specialized press say on our products and the opinion of our
customers. |
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YOGITECH's invited talk on faultRobust at the AEESF 2008 in Stuttgart
03/03/2008
YOGITECH showing achievements of AMSvkit at CDNLive!
Silicon Valley 2007
10/09/2007
YOGITECH participates at ARM Developers' Conference
20/09/2006
YOGITECH
faultRobust
technology featured on 'Automotive Design Line'
12/09/2006
YOGITECH brings its VIP experience
into the first Flexray Verification Environment available in the market
12/09/2006
YOGITECH demonstrates the AMSvkit at CDNLive! Silicon Valley
30/08/2006
YOGITECH 'blesses' the introduction of
Universal Verification Components from Cadence
07/08/2006
YOGITECH participates at IEEE International On-Line Testing Symposium
07/07/2006
YOGITECH at CDNLive! Emea 2006, in Nice,
France
21/06/2006
YOGITECH participates at Sea World Congress, in Detroit, US
29/03/2006
YOGITECH introduces the
technology faultRobust
14/02/2006
YOGITECH publishes on Embedded Star
10/11/2005
YOGITECH partecipates at Same 2005, Sophia Antipolis
30/09/2005
YOGITECH
participates at CDNLIVE!, Silicon Valley
05/09/2005
YOGITECH participates
at IOLTS, in Saint Raphael
04/07/2005
YOGITECH raises 1 million euros in early stage venture capital
26/05/2005
YOGITECH partecipates at ICMTD,
in Giens
16/05/2005
YOGITECH invited talk at CLUB V,
in Santa Clara
08/05/2005
YOGITECH invited talk at CLUB V,
in Sassenage
16/03/2005
YOGITECH publishes on 'Automotive
Design Line'
24/02/2005
YOGITECH participates at DATE, in
Munich (Germany)
22/02/2005
YOGITECH participates at ClubV,
in Munich
20/02/2005
Design and Reuse publishes the
paper «A comprehensive approach for verification of OCP-based
SoCs» by YOGITECH
09/02/2005
YOGITECH invited
talk at IP/SOC in Grenoble
02/12/2004
YOGITECH invited talk at
Verification Process Automation (VPA) seminar series
14/10/2004
YOGITECH invited
talk at GSPx in Santa Clara
17/09/2004
YOGITECH and Verisity invite you
at the new VPA Seminar series
03/09/2004
YOGITECH invited talk at ClubV,
in Santa Clara
09/03/2004
YOGITECH and Verisity at
Next-Generation Verification Seminars
22/09/2003
YOGITECH and ARM made a joint
presentation at the ARM Automotive
Conference
26/11/2002
YOGITECH and Verisity teach
advanced verification methodologies
20/09/2002
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 P R E S S R O O M |
 Testimonials |
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YOGITECH's
Analog Mixed Signal Verification Kit enabled us to reliably verify our
Digital and Analog Mixed-Signal SoC's within in a unified environment
that is familiar to the System on Chip verification engineers.
We have successfully validated complex analog interfaces (including
power management) and IP applying exactly the same techniques and
methods traditionally applied on their digital equivalents.
YOGITECH's automated, metrics-driven coverage methodology increased
verification quality and accelerated the entire process.
Robin Wilson
Design Department Manager,
Design for Qualification, STMicroelectronics |
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YOGITECH's
OCP eVC, with its excellent documentation and
support, proved to be effective and reliable in quickly verifying our
core based ASICs.
Andreas Dieckmann
Verification Manager of Siemens AG |
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The
high verification quality of our OMAP platform has depended heavily on
our use of the YOGITECH OCP eVerification
Component.
Vincent Gillet
OMAP Verification Manager of Texas Instruments |
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YOGITECH
has shown a strong commitment to both OCP-IP and our Functional
Verification Working Group. Their tremendous work is a further
illustration of the thriving robust infrastructure surrounding OCP and
the tremendous support and adoption throughout the industry. We are
grateful to YOGITECH for their contribution.
Ian Mackintosh
President of OCP-IP |
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As
OCP IP GSC Member (Governing Steering Committee) Texas Instruments has
been a leading customer for the OCP eVC and has
successfully adopted this verification tool in several key designs. We
worked closely with YOGITECH as an early adopter of this product to get
the best results improve and enable re-use of our verification platform.
Ziad Mansour
OMAP Hw Program Manager of Texas Instruments |
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