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YOGITECH, founded in
2000, is a company with a solid and proven experience
in the design and verification of digital and mixed-signal
System-on-Chip and in fault-tolerant integrated circuits.
Headquartered in Pisa with offices in Nice, YOGITECH
is an independent company with a Share Capital of 450
thousands Euros, privately owned by its founders and
by financial partners such as Sici Toscana Venture Fund
and the Chamber of Commerce of Pisa.
YOGITECH offers a catalogue of Verification IPs to shorten
time-to-production of projects based on standard protocols,
like ATAPI, LIN and CAN. The portfolio also includes
the Analog Mixed Signal Verification Kit (AMSvKit)
and the OCP 2.1 eVC, the only
complete solution currently available in the market
for the verification of OCP based modules and systems,
successfully adopted by major semiconductor companies
in Europe, US and Asia.
YOGITECH is part of the Cadence OpenChoice Program,
ARM Technology Access Partner, Sponsor Member of the
OCP-IP and Review Member of Spirit Consortium.
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| ARM Technology
Access Partnership
YOGITECH's distinguishing expertise in the ARM Community
is its verification and design for robustness competencies,
especially for automotive applications. Belonging to
the ARM Connected Community, the ARM Technology Access
Partners (ATAPs) is a network of independent IC design
centres, seven of which are in Europe, audited and approved
by ARM according to their competence and experience.
ATAPs have direct access to ARM technical support and
are constantly updated to ARM's design kits, tools,
processor models and debug environments. YOGITECH was
appointed an ATAP in Q4 of 2001 and it was the first
ATAP in Italy.

Open Choice Program
YOGITECH is part of the OpenChoice program
that enables interoperability and facilitates open collaboration
with leading IP providers to build, validate, and deliver
accurate models for Cadence design and verification
solutions.
The program aims to ensure IP quality, integration,
and provides engineers access to a broad IP offering
through a complete IP catalog. This optimizes the electronics
design chain and accelerates customer time to market.

Cadence Verification Alliance
YOGITECH is a Cadence Incisive Plan-to-Closure
Methodology–Qualified
Verification Alliance member and has demonstrated expertise
in one or more
of the methodology’s four key elements: verification
planning and
management, the Universal Reuse Methodology, assertion-based
and formal
verification, and/or system-level verification.


OCP International Partnership
YOGITECH is a Sponsor Member of OCP International
Partnership (OCP-IP), a non-profit semiconductor industry
consortium created to administer the support, promotion
and enhancement of the Open Core Protocol (OCP).
OCP is the only fully supported, openly licensed, complete
interface socket for intellectual property (IP) cores.
YOGITECH’s products portfolio includes OCP
2.1 eVC, the only complete solution
for verifying OCP systems which is successfully adopted
by major semiconductor companies in Europe, US and Asia.


Spirit Consortium
YOGITECH is Review Member of Spirit Consortium,
an industry level cooperation in developing standards
for IP description as well as tools to raise automation
levels, cut costs, improve ease-of-use, increase flexibility
in IP selection and integration. The consortium covers
EDA tool vendors, IP providers and integrated device
manufacturers involving many leading names in the IP
supply chain.
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| YOGITECH is addressing
its products offering on three main streams leveraging
the expertise acquired in design and verification support
activities along the years.
The Verification IPs (VIPs)
catalogue is currently based on the functional verification
methodology provided by Specman Elite, but an extension
of the catalogue to different methodologies and verification
languages like SystemVerilog are in the roadmap. The
catalogue includes VIPs for CAN
2.0A/B and LIN 2.0 (automotive
applications), ATAPI (storage applications)
and OCP 2.1 (set-top box, printers,
games, video recorders, mobile phones, DTV, wireless
LAN). More VIPs will be added
by the end of the year.
The Analog Mixed Signal Verification Kit (AMSvKit)
is a very innovative approach that allows a meaningful
step forward in the verification of analog mixed signal
applications overcoming the drawbacks of traditional
approaches. It includes an extensible set of configurable,
plug-and-play pre-verified verification components that
unify Specman Elite and most popular mixed-signal simulators
to create an Object-Oriented mixed-signal functional
verification environment.
faultRobust is the innovative technology
for addressing and achieving fault robustness in Integrated
Circuits. It provides a set of IPs,
tools and methodologies for the detection and correction
of faults affecting the different parts of the electronic
equipment or SoC. The emerging safety norm IEC61508
is addressed and all of the different parts composing
the technology are under the certification process of
TÜV-SÜD. Automotive active and passive safety
systems such as Steer-by-wire, Brake-by-wire, ABS, etc.
or more in general applications requiring a high degree
of reliability can dramatically benefit by including
faultRobust.
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P
R O D U C T S |
Verification
IPs |
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YOGITECH's Verification
IPs are scalable, configurable, plug-and-play,
pre-verified and extensible verification environments
that can be readily integrated into your design.
They maintain full compatibility with Cadence Specman
Elite test bench automation tool providing a solid basis
in order to realize a complete, reliable and re-usable
verification strategy increasing verification's team productivity
and product's quality. All the VIPs are interoperable
with further releases of Cadence Specman Elite, avoiding
eventual work misalignments between verification teams
and projects.
YOGITECH's proven protocol expertise assures a high reliability
of its VIPs that are all eReuse Methodology (eRM)
compliant. YOGITECH's VIPs are exhaustively
documented and tested. Through YOSS (YOGITECH Online Support
Services), the company provides online support, documentation
downloads, FAQ, examples and enquiries in a timely manner. |
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P
R O D U C T S |
faultRobust |
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YOGITECH's faultRobust
is the technology for addressing and achieving
fault robustness in Integrated Circuits.
It provides a set of IPs, tools and methodologies for
the detection and correction of faults affecting the different
parts of the electronic equipment or SOC. Each fRIP
can be stand-alone, protecting a particular component
such as CPU, memory system and peripherals, or it can
be combined with other fRIPs for a complete
solution.
YOGITECH's faultRobust technology optimizes
costs by minimizing gate count, software overhead and
power consumption; it reduces the common mode effects
by adding diversity; it minimizes performance impact;
offering a platform-based modular and reusable approach;
it increases diagnostic capability; and it addresses the
emerging norm IEC 61508, thus providing
guidelines and a methodology for a system to be IEC 61508
adherent. |
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YOGITECH's Analog Mixed
Signal Verification Kit (AMSvkit) enables
an automated, coverage-driven verification environment
and methodology for top-and block-level mixed-signal designs.
The AMSvKit comprises an extensible set
of configurable, plug-and-play pre-verified verification
components that unify Specman Elite and a mixed-signal
simulator to create an Object-Oriented mixed-signal functional
verification environment.
The greatest obstacle to a System-on-Chip design team's
success is verification. Combine the
challenges of digital verification with the increasing
integration of larger and more sophisticated analog circuits
and the problem is getting exponentially worse. This trend
not only presents a challenge to the verification engineer,
but to the industry as a whole.
To date, the use of hand-coded models of manually-verified
analog blocks within a digital verification environment
has been sufficient to provide confidence in a mixed-signal
design to sign-off prior to submitting it for fabrication.
However, due to greater levels of integration, changes
in process technology and increasing market pressures
and risks, an automated and metric-driven methodology
is now required. |
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| Electronic systems are
nowadays the result of the convergence of different
technologies. Therefore a combination of experience,
techniques, tools and a proper contact network is mandatory
to meet market expectations.
By working with YOGITECH, customers leverage on the
company's solid partnership with top-tier EDA tool vendors.
Years of experience dealing with world-wide customers
and a proven track of right-first-time designs make
YOGITECH reliable for any kind of IC design.
Projects at YOGITECH are managed by specifications,
timescale and budget, previously agreed with clients.
This disciplined yet flexible approach combines with
YOGITECH's methodology, skills and know-how, delivering
customer satisfaction and business renewal. YOGITECH
is actively involved in SoCs or ASICs design&verification,
including implementation or re-use of IP blocks (digital,
analogue and verification), providing point solutions
and filling resource shortfall. |
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S
E R V I C E S |
System-on-Chip |
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Systems-on-Chip are one
of the biggest challenges engineers ever faced. They
are the result of a mix of microprocessors, memories,
busses, architectures, communication standards, protocol
processors, interfaces
and other intellectual property components where system
level considerations such as power optimization, synchronisation,
testability, conformance and verification are crucial.
YOGITECH's outstanding experience with CPUs interconnect
standards and protocols make it easier to match all
system requirements. YOGITECH’s approach always
begins with a fully detailed verification plan and it
is based on a strong interaction between digital and
analogue expertises and the use of the most advanced
verification techniques.
YOGITECH's involvement into a project can span from
specs to tape out (all intermediate steps included),
working independently or in team with the customer.
YOGITECH's expertise includes design of customized IPs
providing highest-quality deliverables such as datasheets,
characterization layout constraints, coverage reports,
implementation, verification scripts. YOGITECH’s
design track record includes projects for the global
worldwide leaders SIPs and OEMs in the automotive, biomedical
and telecom sector. |
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